1. Technical Field
The present invention relates to a voltage selection circuit, an electrophoretic display apparatus, and an electronic device.
2. Related Art
One known example of an active-matrix electrophoretic display apparatus is one that includes a switching transistor and a memory circuit (static random access memory (SRAM)) in a pixel (see, for example, JP-A-2003-84314). The display apparatus described in this patent document has a configuration in which a microcapsule incorporating charged particles is attached on a substrate where a switching transistor and a pixel electrode are formed. This configuration displays an image by controlling the charged particles using an electric field generated between the pixel electrode and a common electrode between which the microcapsule is sandwiched.
The present applicant proposes in JP-A-2008-268853 an improvement of the electrophoretic display apparatus described in the above-mentioned JP-A-2003-84314. With this electrophoretic display apparatus, an operation of writing an image signal to a latch circuit and an operation of applying a voltage to an electrophoretic element and displaying an image can be independently controlled. For example, the power supply voltage of the latch circuit can be 5 V in writing an image signal to suppress a load of a driving circuit and power consumption, whereas the power supply voltage of the latch circuit can be 15 V in displaying an image to acquire a high contrast. It is conceivable to use such operations in the electrophoretic display apparatus described in the above-mentioned patent document JP-A-2003-84314.
To use different power supply voltages for a latch circuit in writing an image signal and in displaying an image, as described above, it is necessary to have a voltage selection circuit, as illustrated in FIGS. 18A and 18B, in a power supply system for supplying a power supply voltage to the latch circuit. A voltage selection circuit 641 illustrated in FIG. 18A and a voltage selection circuit 642 illustrated in FIG. 18B are each a circuit that outputs a potential selected from among a high-level driving potential VH (e.g., 15 V), a high-level pixel writing potential VL (e.g., 5 V), and a battery potential VB (e.g., 2 V) from an output terminal Nout.
The voltage selection circuit 641 illustrated in FIG. 18A includes a first switching circuit SC11, a second switching circuit SC12, and a third switching circuit SC13. The first switching circuit SC11 includes a positive channel metal-oxide semiconductor (P-MOS) transistor PM1 and a level shifter LS1. The second switching circuit SC12 includes a P-MOS transistor PM21 and a level shifter LS21. The third switching circuit SC13 includes a P-MOS transistor PM31 and level shifter LS31.
In the voltage selection circuit 641, a high-voltage transistor is, of course, used in the P-MOS transistor PM1. Additionally, because the drain terminal of each of the P-MOS transistor PM1, the P-MOS transistor PM21, and the P-MOS transistor PM31 is connected to a common output line DL (output terminal Nout), a high-voltage transistor is also used in each of the P-MOS transistor PM21 and the P-MOS transistor PM31 to prevent the entry of a high-level driving potential VH output from the first switching circuit SC11. Furthermore, it is also necessary to use a high-voltage transistor in each of the level shifter LS21 connected to the gate terminal of the P-MOS transistor PM21 and the level shifter LS31 connected to the gate terminal of the P-MOS transistor PM31 to supply the high-level driving potential VH to the gate terminal of each of the P-MOS transistor PM21 and the P-MOS transistor PM31.
The voltage selection circuit 642 illustrated in FIG. 18B includes the first switching circuit SC11, which is the same as that used in the voltage selection circuit 641, a second switching circuit SC22, and a third switching circuit SC23. The second switching circuit SC22 includes an negative channel MOS (N-MOS) transistor NM1 and the level shifter LS21. The third switching circuit SC23 includes an N-MOS transistor NM2 and a level shifter LS32.
In the voltage selection circuit 642, in which each of the second switching circuit SC22 and the third switching circuit SC23 includes an N-MOS transistor, it is also necessary to use a high-level transistor in each of the N-MOS transistor NM1 and the N-MOS transistor NM2 to prevent the entry of the high-level driving potential VH output from the first switching circuit SC11. In contrast, because it is only necessary that the gate-source voltage (Vgs) of the N-MOS transistor NM2 be a predetermined voltage higher than a threshold voltage, the level shifter LS32 in the third switching circuit SC23 can be one that raises the battery potential VB to the high-level pixel writing voltage VL, for example. Accordingly, a low-voltage transistor of approximately 5 to 6 V can be used in the level shifter LS32. The circuitry area of the voltage selection circuit 642 can be smaller, although slightly, than that of the voltage selection circuit 641 illustrated in FIG. 18A.
As described above, both when a P-MOS transistor is used in a switching element and when an N-MOS transistor is used therein, a plurality of high-voltage transistors is necessary, and this presents a problem of a large circuitry area. In addition, because a high-voltage transistor causes a large leakage current, the high-voltage transistor is disadvantageous in terms of power consumption. Furthermore, such a large-size high-voltage transistor may restrict a circuitry layout.